For more than three decades, the continued miniaturization of silicon metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicted for three decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor (MOS) transistors are beginning to reach their traditional scaling limits [A concise summary of near-term and long-term challenges to continued CMOS scaling can be found in the “Grand Challenges” section of the 2002 Update of the International Technology Roadmap for Semiconductors (ITRS). A very thorough review of the device, material, circuit, and systems limits can be found in Proc. IEEE, Vol. 89, No. 3, March 2001, a special issue dedicated to the limits of semiconductor technology].
Since it has become increasingly difficult to improve MOSFET and therefore complementary metal oxide semiconductor (CMOS) circuit performance through continued miniaturization, methods for improving performance without scaling have become critical. One general approach for doing this is to increase carrier (electron and/or hole) mobilities. This can by done by either: (1) introducing an appropriate strain into the Si lattice; (2) by building MOSFETs on Si surfaces that are oriented in directions different than the conventional <100> Si; or (3) a combination of (1) and (2).
As far as approach (1) is concerned, several methods such as, for example, strained Si on a relaxed SiGe buffer layer and strained Si on relaxed SiGe on insulator have been described for producing Si under biaxial tensile strain. This has been shown to significantly enhance electron mobilities, but requires high Ge fractions to only mildly enhance hole mobilities in <100> Si.
In terms of approach (2), it is well known that hole mobilities in <110> Si are more than twice that of conventional <100> Si. However, electron mobilities in relaxed (unstrained) <110> Si are degraded by about a factor of two compared to the <100> case. This has led to the invention of a somewhat complex “hybrid” scheme for integrating pFETs built in <110> Si and nFETs built in <100> Si [M. Yang et al., IEDM Technical Digest, pg. 453, 2003]. Although this hybrid approach benefits pFETs significantly, it typically has no benefit for nFETs.
There is a significant advantage to an approach that can significantly enhance both electron and hole mobilities, while at the same time avoiding the complexities of hybrid crystalline orientation schemes.